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<STRONG><U>III.5 The 8051 Instruction Set</U></STRONG>
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<NOBR>ASEM-51</NOBR> implements all 8051 machine instructions including
generic jumps and calls. The assembler implements two instructions
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<BLOCKQUOTE>
<STRONG><PRE>
JMP  &lt;address&gt;
CALL &lt;address&gt;
</PRE></STRONG>
</BLOCKQUOTE>
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that do not represent a specific opcode: generic jump and call.
These instructions will always evaluate to a jump or call, not necessarily
the shortest, that will reach the specified address.<BR>
JMP may assemble to SJMP, AJMP or LJMP, while CALL can only evaluate to
ACALL or LCALL. Note that the assembler decision may not be optimal. For
code addresses that are forward references, the assembler always generates
LJMP or LCALL respectively. However, for backward references this is a
powerful tool to reduce code size without extra trouble.
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With the $PHILIPS control, <NOBR>ASEM-51</NOBR> can be switched to the reduced
instruction set of the Philips 83C75x family of microcontrollers. This disables
the LJMP, LCALL, and MOVX instructions as well as the XDATA and XSEG pseudo
instructions, and generic jumps and calls will always assemble to absolute
addressing.
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The rest of the 8051 instruction mnemonics is listed in
<A HREF="append_d.htm">Appendix D</A>.
Appendices <A HREF="append_i.htm">I</A> and <A HREF="append_j.htm">J</A> are
containing tables of all 8051 instructions with their opcodes, mnemonics,
arguments, lengths, affected flags and durations.
The comprehensive example program DEMO.A51 provided shows all the 8051
instructions in a syntactical context.
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For detailed information on the Intel <NOBR>MCS-51</NOBR> architecture and
instruction set refer to the
<A HREF="mcs51man.htm">MCS&reg; 51 Microcontroller Family User's Manual</A>.
(Requires full Internet access!)
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All <NOBR>MCS-51</NOBR> instruction mnemonics are copyright &copy; by
Intel Corporation!
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